In connection with the ongoing reduction in the size of semiconductor devices, the cross section of metal wirings is being reduced, and thus current density increases. This causes a severe problem of low reliability in metal wirings due to electromigration (EM). Accordingly, copper, which has excellent reliability as well as a lower specific resistance than aluminum, may be used for the material in metal wirings.
However, copper wirings cannot be fabricated using a dry etching process, due to difficulty in producing highly-volatile compounds. Therefore copper wirings are mainly produced using a damascene process. Hereinafter, a related single damascene process will be described with reference to the accompanying drawings.
FIGS. 1A to 1F are sectional views for individual steps in a related single damascene process. First, as shown in FIG. 1A, a lower insulating film 10 may be deposited over upper portion of a semiconductor substrate. The lower insulating film 10 may be selectively etched to form vias 11.
Next, as shown in FIG. 1B, tungsten 20 may be deposited over the entire surface of the lower insulating film 10 and the vias 11 (shown in FIG. 1A). Thereafter, as shown in FIG. 1C, tungsten plugs 21 may be formed by performing a chemical mechanical polishing (CMP) process to remove tungsten 20 excessively deposited over the lower insulating film 10.
As shown in FIG. 1D, an upper insulating film 30 may be deposited over the entire surface of upper portion of the lower insulating film 10. Next, as shown in FIG. 1E, the upper insulating film 30 may be selectively etched to form trenches 31.
As shown in FIG. 1F, copper 40 may be deposited over the entire surface of the upper insulating film 30 and the trenches 31. Next, as shown in FIG. 1G, copper wirings 41 may be formed by performing a CMP process to planarize the upper surface of the trenches 31.
In the above steps, as shown in FIG. 1C, while over-polishing is carried out to completely remove tungsten excessively deposited over the upper portion of the lower insulating film 10, the over-polishing may etch the lower insulating film 10. In this case, the lower insulating film 10 may be more etched in an area A, having higher pattern density, than in an area having lower pattern density (which is called “pattern density effect”). As a result, as shown in FIG. 1G, a short-circuit B may develop between copper wirings adjacent to the area A having the higher pattern density.
In addition, when the lower insulating film is etched, the tungsten plugs are more polished than the lower insulating film since the tungsten plugs have a higher polishing rate than that of the lower insulating film. This causes another problem, of poor contact between the tungsten plugs and the copper wirings during formation of the copper wirings. This is called “dishing”.